(1) Field of the Invention
The present invention relates to error correction, and more specifically, to an error correction device used for optical disks having a data structure composed of a main data unit and a parity unit.
(2) Description of the Prior Art
In recent years, DVDs (digital versatile discs) and CD-ROMs (compact disc-read-only memories) for recording digital data at high densities have come to be widely used. The digital data, which are recorded or read by a laser, are very small in size. No matter how carefully these media may be fabricated or handled, it is difficult to prevent them from getting fingerprints or blemishes on their surface.
Hence, the use of error correcting technology is essential. However, in such a case where 1-bit parity is merely appended to every 7-bit main data, if an error arises, its presence is known but its location and the original data remain unknown. Moreover, if two errors arise, their occurrence itself is unknown. To solve this problem, as shown in FIGS. 1 and 2, error correction is performed by providing data with parity having a complicated structure in the vertical and the horizontal direction. According to this system, even if several errors arise, they will be found in real time and corrected.
There have been various techniques developed as methods for appending parity, one of them being RS code correction which comes down error correction to a question of solving a numerical formula. Since RS code correction is a known art shown in FUGO RIRON NYUMON or Introduction to the Theory of Codes written by Iwatare and published by Shoseido, JISSEN AYAMARI TEISEI GIJUTU, or A Hands-on Technique of Error Correction published by TRICEPTS, and the like, its description will be omitted.
In optical disks such as DVDs and CD-ROMs, error correction of data is performed in compliance with individual data formats.
The following is a description of error correction for a DVD. The data format in one sector is shown in FIG. 1, and the data format in one block including error correcting codes (ECCs) is shown in FIG. 2. As shown in FIG. 1, one sector includes a header, main data, and an error detecting code (EDC). The block including the ECCs shown in FIG. 2 contains the sector shown in FIG. 1, and has product codes with inner code parity for horizontal error correction and outer code parity for vertical error correction. (In the present specification, as a rule, the sector shown in FIG. 1+the inner code parity on the right side in FIG. 2 is referred to as a sector).
In an error correction device for DVDs, it is general that demodulated data are temporarily written in the buffer memory and read later in order to execute error correction for the data in the buffer memory because error correction in real time takes much time, considering it is done by an electronic device, and has to be repeated until no error is left. In this case, there are horizontal error correction with inner code parity and vertical error correction with outer code parity.
In horizontal error correction for consecutive main data such as image data, syndrome calculation is performed every code word (string) (consisting of 172-byte data and 10-byte inner code parity) to detect an error-containing code, and error correction is performed by calculating the position and value of the error, based on the data of the detected code. In vertical error correction, syndrome calculation is performed every code word (consisting of 192-byte data and 16-byte outer code parity) to detect an error-containing code, and the position and value of the error are calculated, based on the data of the detected code. Following error correction repeated for a predetermined number of times in the horizontal direction first and then in the vertical direction, error detection is performed in order to check to see that no error remains in the data (or that the error correction is successfully done) by using each EDC. If no error is detected, this means that the error correction is complete.
Then, data in the buffer memory whose error has been corrected are transmitted downstream, and data in the next sector obtained from upstream are written in the buffer memory.
A prior art error correction device is shown in FIG. 3. This device comprises a system control unit 1 which controls the entire system, a DMA control unit 2 which controls DMA (direct memory access) transfer described below between buffer memory and each unit, a bus control unit 3, a buffer memory 4 which stores demodulated data, a syndrome calculator 5 for generating syndrome that is an equation to be solved for error correction, an error corrector 6 which performs error correction by calculating the position and value of an error, based on the syndrome generated by the syndrome calculator 5, and an error detector 7 which detects the presence or absence of an error in the data which has been subjected to error correction, or which checks to see that all errors have been corrected. The bus control unit 3, the buffer memory 4, the syndrome calculator 5, the error corrector 6, and the error detector 7 are connected with each other via a data bus 11.
A DMA command 12 is transmitted from the system control unit 1 to the DMA control unit 2 in order to provide instructions to execute DMA. (The drawing shows the signal line of the command 12 for the sake of convenience. This holds true for the other signals). A DMA request 13 is transmitted from the DMA control unit 2 to the bus control unit 3 in order to request DMA. A buffer memory access signal 14 is transmitted to execute the reading or writing of data from or to the buffer memory 4. A syndrome data supply signal 15 indicates the supply of data in the buffer memory 4 to the syndrome calculator 5. Syndrome 16 is the product in the syndrome calculator 5.
An access request signal 17 is transmitted from the error corrector 6 to the bus control unit 3 in order to request access to the buffer memory 4. An error corrector access signal 18 is transmitted to execute the reading or writing of data from or to the error corrector 6. An error correction completion signal 19 indicates that error correction is completed in the error corrector 6. An error detector data supply signal 20 indicates the supply of data from the buffer memory 4 to the error detector 7. An error detection signal 21 indicates whether or not an error has been detected by the error detector 7.
FIG. 4 shows the procedure of horizontal error correction in one sector.
The procedure of horizontal error correction in one sector in the prior art error correction device will be described as follows with reference to FIGS. 3 and 4.
Step (a-1): the system control unit 1 outputs the DMA command 12 to the DMA control unit 2 so as to provide instructions to transfer data equivalent to one code word×13 times from the buffer memory 4 to the syndrome calculator 5.
Step (a-2): the DMA control unit 2 outputs the DMA request 13 to the bus control unit 3 so as to request the data transfer from the buffer memory 4 to the syndrome calculator 5.
Step (a-3): the bus control unit 3 puts the data bus 11 in commission, and outputs the buffer memory access signal 14 and the syndrome data supply signal 15 to the buffer memory 4 and the syndrome calculator 5, respectively, so as to execute the data transfer from the buffer memory 4 to the syndrome calculator 5.
Step (a-4): the syndrome calculator 5 performs error detection every transferred code word, and outputs the syndrome 16 to the error corrector 6 if there is an error.
Step (a-5): the error corrector 6 calculates the position and value of the error, based on the syndrome 16. In order to correct an error in data on the buffer memory 4, the error corrector 6 provides the bus control unit 3 with the access request signal 17, thereby requesting readout of the error-containing data.
Step (a-6): after putting the data bus 11 in commission, the bus control unit 3 outputs the buffer memory access signal 14 and the error corrector access signal 18 to the buffer memory 4 and the error corrector 6, respectively, reads error-containing data from the buffer memory 4, and supplies the data to the error corrector 6.
Step (a-7): after correcting the error in the data supplied, the error corrector 6 transmits the access request signal 17 to the bus control unit 3 again so as to request writing of the error-corrected data in the buffer memory 4.
Step (a-8): after putting the data bus 11 in commission, the bus control unit 3 reads the error-corrected data from the error corrector 6 and overwrites the data in the buffer memory 4. At the same time, the error corrector 6 transmits the correction completion signal 19 to the system control unit 1.
Step (a-9): in order to check to see that the corrected data contain no more error, the system control unit 1 transmits the DMA command 12 to the DMA control unit 2 so as to provide instructions to transfer the data from the buffer memory 4 to the error detector 7.
Step (a-10): the DMA control unit 2 outputs the DMA request 13 to the bus control unit 3 so as to request the data transfer from the buffer memory 4 to the error corrector 7.
Step (a-11): after putting the data bus 11 in commission, the bus control unit 3 outputs the buffer memory access signal 14 and the error detector data supply signal 20 to the buffer memory 4 and the error detector 7, respectively, so as to execute the data transfer from the buffer memory 4 to the error detector 7.
Step (a-12): the error detector 7 performs error detection for the data transferred, and transmits the error detection signal 21 to the system control unit 1 in order to inform whether an error has been detected or not.
Through these steps, the horizontal error correction for one sector is complete.
In the same manner, horizontal error correction is executed for the subsequent 15 sectors including the outer code parity unit so as to complete the horizontal error correction for one block. If no error is detected from all sectors, the error correcting operation is complete; if there is an error detected even from one sector, the next process including vertical error correction will be executed.
The above-described prior art method, however, takes much time in a series of operations: the syndrome calculation by the syndrome calculator 5, the error correction by the error corrector 6, and the error detection by the error detector 7 done in this order. Above all, it is time-consuming to access the buffer memory 4 as storing means and to read data therefrom repeatedly because these operations are not performed like electric circuit but often mechanically done by relative movement between the readout means and the buffer memory 4.
Furthermore, a significant improvement in accuracy of reading and writing digital data to and from CD-Rs and other similar media in recent years has reduced the necessity of error correction by the error corrector. Nevertheless, the data in the head portions, which have been checked to contain no error, are often subjected to error detection by the error detector. Consequently, error correction and error detection, which could be processed in parallel in most cases, are processed separately in time, thereby wasting much time.
The error correction and the error detection are not satisfactory in consideration of probable higher densities and more rapid readout of DVDs and other recording media in the future.
In high-speed reproduction performed to check the position of specific image data or to inspect their contents, it is not always necessary to reproduce image data completely. On the other hand, it is usually necessary for data relating to the programs of the CPU to be reproduced in a perfect form even if it takes much time. Thus, error correction must be performed at different levels, which have not been satisfactorily done so far.
Hence, it has been expected to develop an error correction device which performs error correction more accurately and faster in accordance with required performance levels.